I. Field
The present disclosure relates generally to electronics, and more specifically to a digital phase-locked loop.
II. Background
Phase-locked loops (PLLs) are an integral part of many electronics circuits and are particularly important in communication circuits. For example, digital circuits use clock signals to trigger synchronous circuits, e.g., flip-flops. Transmitters and receivers use local oscillator (LO) signals for frequency upconversion and downconversion, respectively. Wireless devices (e.g., cellular phones) for wireless communication systems typically use clock signals for digital circuits and LO signals for transmitters and receivers. The clock and LO signals are generated with oscillators and their frequencies are often controlled with PLLs.
A PLL typically includes various circuit blocks used to adjust the frequency and/or phase of an oscillator signal from an oscillator. These circuit blocks may consume a relatively large amount of power, which may be undesirable for portable devices such as cellular phones. There is therefore a need in the art for techniques to reduce power consumption of a PLL without sacrificing performance.